high speed cmos 1 megabit programmable and erasable rom 128k x 8 bit flash perom description: the turbo ic 29c010 is a 128k x 8 flash programmable and erasable read only memory (perom) fabricated with turbo ics proprietary, high reliability, high performance cmos technology. its 1024k bits of memory are organized as 128k by 8 bits. the device offers access time of 120 ns with power dissipation below 330 mw. the 29c010 has a 128 bytes sector program operation en- abling the entire memory to be programmed typically in less than 10 seconds. during a program operation, the address and a complete sector (128 bytes) of data are internally latched, freeing the address and data bus for other micro- processor operations. the programming process is auto- matically controlled by the device using an internal control timer. data polling on i/o7 or a toggle bit can be used to detect the end of a programming cycle. in addition, the 29c010 includes an user-optional software data write mode offering additional protection against unwanted (false) write. the 29c010 does not require a separate high voltage to program the device. 5 volts is all that is required. features: ? 120 ns access time ? 5 volt only reprogramming ? sector program operation single cycle reprogram (erase & program) 1024 sectors (128 bytes/sector) internal address and data latches for 128 bytes ? automatic sector programming operation internal control timer ? fast program times page program cycles: 10 ms typical time to rewrite complete memory: 10 s typical byte program cycle time: 80 s ? software data protection ? low power dissipation 60 ma active current 100 a cmos standby current ? direct microprocessor end of program detection data polling ? high reliability cmos technology endurance: 10,000 cycles data retention: 10 years ? cmos and ttl compatible inputs and outputs ? single 5v 10% power supply for read and program- ming operations ? jedec approved byte pinout pin configurations: 4 3 5 2 1 6 7 8 9 10 11 12 13 30 31 32 a14 a13 a8 a9 a11 oe a10 ce i/o7 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a15 a12 a16 nc vcc we nc 32 pins plcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 vcc we nc a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 31 30 29 28 27 26 25 24 23 22 21 20 19 oe ce i/o6 i/o4 gnd i/o1 a0 a1 i/o0 i/o2 i/o3 i/o5 i/o7 a10 a11 a8 a14 we nc a15 a7 a6 a12 a16 vcc nc a13 a9 32 pins pdip 32 pins tsop 14 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 29 30 31 32 i/o4 i/o3 i/o2 gnd 15 16 17 18 a2 a3 a5 a4 29c010 advance information turbo ic, inc.
chip enable (ce) the chip enable input must be low to enable all read/program operations on the device. by setting ce high, the device is disabled and the power consumption is extremely low with the standby current below 100 a. addresses (a0 - a16) the addresses are used to select an 8 bits memory location during a program or read operation. pin description output enable (oe) the output enable input activates the output buffers during the read op- erations. write enable (we) the write enable input initiates the programming of data into the memory. data input/output (i/o0-i/o7) data input/output pins are used to read data out of the memory or to program data into the memory. device operation read the 29c010 is accessed like a static ram. read operations are initiated by both ce and oe on low and terminated by either ce or oe returning high. the outputs are at the high impedance state whenever ce or oe returns high. the two line control architecture gives designers flexibility in preventing bus contention. program a program cycle is initiated when ce and we are low and oe is high. the address is latched internally on the falling edge of the ce or we, which- ever occurs last. the data is latched by the rising edge of ce or we, whichever occurs first. once a programming cycle has been started, the internal timer automatically generates the program sequence to the comple- tion of the program operation. sector program operation the device is reprogrammed on a sector basis. when a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. any byte that is not loaded during the programming of its sector will be erased to read ffh. the programming operation of the 29c010 allows 128 bytes of data to be serially loaded into the device and then simulta- neously written into memory during the internally generated program cycle. after the first byte has been loaded, successive bytes of data must be loaded until the full sector of 128 bytes is loaded. each new byte to be written must be loaded within 300 s of the previously loaded byte. the sector address defined by the addresses a7 - a16 is latched by the first ce or we falling edge which initiates a program cycle and they stay latched until the completion of the program cycle. any changes in the sector ad- dresses during the load-program cycle will not affect the initially latched sector address. addresses a0 - a6 are used to define which bytes will be loaded within the 128 bytes sector. the bytes may be loaded in any order that is convenient to the user. the content of a loaded byte may be altered at any time during the loading cycle if the maximum allowed byte-load time (300 s) is not exceeded. all the 128 bytes of the page are serially loaded and are programmed in a single 10 ms program cycle data polling the 29c010 features data polling to indicate the completion of a program cycle to the host system. during a program cycle, an attempted read of the last byte loaded into the page will result in the complement of the loaded byte on i/o7, i.e., loaded 0 would be read 1. once the program cycle has been completed, true data is valid on all outputs and the next cycle may be started. data polling may begin at any time during the programming cycle. toggle bit in addition to data polling the 29c010 provides another method for deter- mining the end of a programming or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. chip clear the content of the entire memory array of the 29c010 may be altered to high by the use of the chip clear operation. by setting ce to low, oe to 12 volts, and we to low, the entire memory array can be cleared (written high) within 20 ms. the chip clear operation is a latch operation mode. after ce, we, and oe get the chip clear process started, the internal chip timer takes over the chip clear operation and ce, oe, or we becomes free to be used by the system for other purposes. hardware data protection the 29c010 has three hardware features to protect the written content of the memory against inadvertent programming: a) vcc threshold detector - if vcc is below 3 v the program capabilities of the chip is inhibited for whatever input conditions. b) noise protection - a we, oe, or ce pulse of less than 10 ns in width is not able to initiate a program cycle. c) write inhibit - holding oe at low, or ce at high, or we at high inhibits the program cycle. software data protection the 29c010 offers a software controlled data program protection feature. the device is delivered to the user with the software data protection dis- abled, i.e., the device will go to the program operation as long as vcc exceeds 3 v and ce, we, and oe inputs are set at program mode levels. the 29c010 can be automatically protected against an accidental write operation during power-up or power-down without any external circuitry by enabling the software data protection feature. this feature is enable after the first program cycle which includes the software algorithm. after this operation is done the program function of the device may be performed only if every program cycle is preceded by the software algorithm. the device will maintain its software protect feature for the rest of its life, unless the software algorithm for disabling the protection is implemented. advance information 29c010 turbo ic, inc.
software algorithm the 29c010 has an internal register for the software algorithm which en- ables the memory to provide the user with additional features: a) software data protect enable a sequence of the three dummy data writes to the memory will activate internal eeprom fuses during the first page write cycle. these eeprom fuses will reject any write attempts of new pages of data, unless the three dummy data writes are repeated at the beginning of any page writes. the timing for the dummy data and addresses must be the same as for a normal program operation. a violation of the three steps program protect sequence in data or address timing and content will abort the procedure and reset the device to the starting point condition. note: software data protect enable procedure must be performed as part of a standard program cycle. if no additional page data is added to the three dummy data writes, the software data protect enable procedure will be aborted. the data protect state will be activated at the end of the pro- gram cycle. 128 bytes of data must be loaded during a software data protection enable cycle. table 1 shows the required procedure for enabling the software data pro- tect: table 1 step mode add .a14-a0 data i/o 7-0 1 page write 5555 hex aa hex 2 page write 2aaa hex 55 hex 3 page write 5555 hex a0 hex 4-131 page write address sector data (128 bytes) b) software data protect disable the software algorithm of 29c010 includes a six step sequence dummy data programming sequence to disable the software data protect feature described in a). the six step sequence shown in table 2 must be per- formed at the beginning of a program cycle. a violation of the six step program sequence in data or address timing and content will abort the procedure and reset the chip to the starting point condition. after a soft- ware data protect disable cycle including the six step sequence has been performed, the 29c010 does not require the use of three dummy loads described in a) for the following program cycle. the device is at the soft- ware data protect disabled state. note: when six step sequence of software data protect disable procedure is performed, if no additional bytes of data is added after the six-step write sequence, the software data protect disable procedure will be aborted. the data protect state will be deactivated at the end of the program period. 128 bytes of data must be loaded during a software data protection dis- able cycle. table 2 shows the required procedure for disabling the software data pro- tect: table 2 step mode add .a14-a0 data i/o 7-0 1 page write 5555 hex aa hex 2 page write 2aaa hex 55 hex 3 page write 5555 hex 80 hex 4 page write 5555 hex aa hex 5 page write 2aaa hex 55 hex 6 page write 5555 hex 20 hex 7-134 page write address sector data (128 bytes) c) software chip clear the software algorithm of 29c010 includes a sequence of six step dummy data writing to perform a chip clear operation. table 3 shows the six step write sequence to perform the software chip clear operation: table 3 step mode add .a14-a0 data i/o 7-0 1 page write 5555 hex aa hex 2 page write 2aaa hex 55 hex 3 page write 5555 hex 80 hex 4 page write 5555 hex aa hex 5 page write 2aaa hex 55 hex 6 page write 5555 hex 10 hex at the end of the six step program sequence shown in table 3, the device automatically activates its internal timer to control the chip erase cycle; typically takes 20 msec. after a software chip clear operation has been completed, all 1024k bit locations of memory show high level at read operation mode. d) software autoclear disable mode this software algorithm disables the internal automatic clear before a pro- gram cycle. table 4 shows the six steps needed to perform the autoclear disable mode. table 4 step mode add.a14-a0 data i/o 7-0 1 page write 5555 hex aa hex 2 page write 2aaa hex 55 hex 3 page write 5555 hex 80 hex 4 page write 5555 hex aa hex 5 page write 2aaa hex 55 hex 6 page write 5555 hex 40 hex 7-134 page write address sector data (128 bytes) program operation using the software autoclear disable mode will reduce programming time to typically 40 s per byte. the program cycle using software autoclear disable mode is usually used after a chip clear or a software chip clear operation. at the end of the six step sequence, the autoclear before program is disabled and will stay that way unless a power- down occurs or the software autoclear enable procedure is initiated. e) software autoclear enable mode automatic page clear before page program can be restored to 29c010 either by vcc power-down or by software autoclear enable mode. table 5 shows the six step page procedure needed to enable software autoclear mode: table 5 step mode add.a14-a0 data i/o 7-0 1 page write 5555 hex aa hex 2 page write 2aaa hex 55 hex 3 page write 5555 hex 80 hex 4 page write 5555 hex aa hex 5 page write 2aaa hex 55 hex 6 page write 5555 hex 50 hex 7-134 page write address sector data (128 bytes) 29c010 turbo ic, inc. advance information
a.c. characteristics - read operation 29c010-1 29c010-2 29c010-3 symbol parameters min max min max min max unit tacc address to 120 150 200 ns output delay tce ce to output 120 150 200 ns delay toe oe to output 70 80 90 ns tdf oe to output 0 40 0 50 0 60 ns in high z toh output hold 0 0 0 ns from address changes, chip enable or output enable whichever occurs first symbol parameter condition min max units icc active vcc ce=oe=vil; all i/o 60 (c) ma current open, min read or 70 (i) ma write cycle time 90 (m) ma isb1 cmos ce=vcc-0.3 v to 100 (c) a standby vcc+1 v 200 (i&m) a current isb2 ttl standby ce=vih, oe=vil, 3 ma current all i/o open, other inputs=vcc max iil input vin=vcc max 1 a leakage current iol output 10 a leakage current vil input low -0.1 -0.8 v voltage vih input high 2 vcc+0.3 v voltage vol output low iol=2.1 ma 0.45 v voltage voh output high ioh=-0.45 ma 2.4 v voltage (c) = commercial (i) = industrial (m) = military tacc address valid address ce oe output high-z toe tce tdf toh output valid high-z a.c. test conditions output load : 1 ttl load and cl=100 pf input rise and fall times : < 10 ns input pulse level : 0.45 v to 2.4v d.c. characteristics absolute maximum stress ranges * a.c. read wave forms recommended operating conditions temperature range : commercial: 0 c to 70 c industrial: -40 c to 85 c military: -55 c to 125 c vcc supply voltage :5 v 10% endurance: 10,000 cycles/byte (typical) data retention : 10 years * absolute maximum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sec- tion of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. temperature storage: -65 c to 150 c under bias: -55 c to 125 c all input or output voltages with respect to vss +6 v to -0.3 v advance information 29c010 turbo ic, inc.
oe address ce we data toes tas tcs tah toeh tch twp tds tblc twc tdh high-z data valid high-z valid oe address ce we data toes tas tcs tah toeh tch twp tds tblc twc tdh high-z data valid high-z valid a.c. write characteristics symbol parameter min max units tas address set-up time 20 ns tah address hold time 100 ns tcs write set-up time 0 ns tch write hold time 0 ns tcw ce pulse width 100 ns twp we pulse width 100 ns toes oe set-up time 10 ns toeh oe hold time 10 ns tds data set-up time 50 ns tdh data hold time 0 ns tblc byte load cycle 0.2 300 s tlp last byte loaded to data polling output 500 s twc write cycle time 10 ms a.c. write wave forms we-controlled a.c. write wave forms ce-controlled 29c010 turbo ic, inc. advance information
page mode write characteristics symbol parameter min max unit twc write cycle time 10 ms tas address set-up time 20 ns tah address hold time 100 ns tds data set-up time 50 ns tdh data hold time 0 ns twp write pulse width 100 ns tblc byte load cycle time 0.2 300 s twph write pulse width high 100 ns oe ce we a0-a6 data twp twph tah tas tds tdh byte-0 byte-1 byte-2 byte address a7-a16 sector address // // // // // // // // // byte- 126 byte-127 page mode write wave forms (1,2,3) note: 1. a7 through a16 must be specify the sector address during each high to low transition of we or ce. 2. oe must be high when we and ce are both low. 3. all bytes that are not loaded within the sector being programmed will be erased to ff. turbo ic, inc. advance information 29c010
data polling characteristics symbol parameter min max unit tdh data hold time 10 ns toeh oe hold time 10 ns toe oe to output delay (1) ns twr write recovery time 0 ns note: 1. see toe specification in ac characteristics - read operation data polling wave forms we ce oe a0-a16 an an an // // // // // // i/o7 twr tdh toe toeh an an high z toggle bit characteristics symbol parameter min max unit tdh data hold time 10 ns toeh oe hold time 10 ns toe oe to output delay (1) ns toeh oe high pulse 150 ns note: 1. see toe specification in ac characteristics - read operation toggle bit wave forms (1,2,3) we ce oe // // // // i/o6 tdh toe high z toeh note: 1. toggling either oe or ce or both will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. turbo ic, inc. 29c010 advance information
turbo ic, inc. 2365 paragon drive, suite i, san jose, ca 95131 phone: 408-392-0208 fax: 408-392-0207 see us at www.turbo-ic.com rev. 3.0 - 10/28/ 01 part numbers & order information 29c010pc-2 speed -1 120 ns -2 150 ns -3 200 ns temperature c -commercial i -industrial m -military package j -plcc p -pdip t -tsop 128k x 8 perom oe ce we ts= 20 ns tp= 200 ns th= 20 ns vh=12.0 v0.5v tp th vh vih vih vil vih vil ts chip clear wave form the content of the 29c010 may be altered to high by the use of the chip clear operation. by setting ce to low, oe to 12 volts, and we to low, the entire memory can be cleared (written high) within 20 ms. the chip clear operation is a latch operation mode. after the chip clear starts, the internal chip timer takes over and completes the clear with- out ce, oe and we being held active. turbo ic products and documents 1. all documents are subject to change without notice. please contact turbo ic for the latest revision of documents. 2. turbo ic does not assume any responsibility for any damage to the user that may result from accidents or operation under abnormal conditions. 3. turbo ic does not assume any responsibility for the use of any circuitry other than what embodied in a turbo ic product. no other circuits, patents, licenses are implied. 4. turbo ic products are not authorized for use in life support systems or other critical systems where component failure may endanger life. system designers should design with error de- tection and correction, redundancy and back-up features. advance information 29c010 turbo ic, inc.
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